A3P600-FGG484

A3P600-FGG484 Descrição geral

The A3P600-FGG484 FPGA, a part of Microchip Technology's ProASIC3 family, is a game-changing device that redefines the possibilities in the field of programmable gate arrays. With an impressive 600,000 system gates, this FPGA delivers unmatched performance and versatility, making it ideal for applications across various industries. Thanks to its revolutionary Flash*Freeze technology, the A3P600-FGG484 boasts incredibly low static power consumption, setting a new standard for energy efficiency in programmable logic devices. The reprogrammable flash technology allows for in-system programming, providing engineers with the flexibility to optimize their designs in real-time. This FPGA comes equipped with 293 user I/Os, opening up a wide range of connectivity options and ensuring seamless integration into different systems. Supporting high-speed interfaces like SPI, I2C, and UART further enhances its adaptability. Moreover, its security features, which include non-volatile key storage and anti-tamper capabilities, demonstrate Microchip Technology's dedication to keeping sensitive data safe and secure. Whether in communications, industrial, or automotive applications, the A3P600-FGG484 offers a reliable and cost-effective solution for designs that demand moderate logic capacity and flexible programming

Características

• High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
• Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI†
• In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced
• Encryption Standard (AES) Decryption (except ARM®-
• enabled ProASIC®3 devices) via JTAG (IEEE 1532–
• compliant)†
• FlashLock® to Secure FPGA Contents
• Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
• 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and
• LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and
• M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
• Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
• RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18)
• ARM Processor Support in ProASIC3 FPGAs
• M1 and M7 ProASIC3 Devices—Cortex-M1 and
• CoreMP7 Soft Processor Available with or without

Especificações